neorv32
:desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. (by stnolting)
riscv-arch-test
By riscv-non-isa
| neorv32 | riscv-arch-test | |
|---|---|---|
| 77 | 8 | |
| 1,453 | 469 | |
| - | 1.5% | |
| 9.9 | 8.7 | |
| 4 days ago | 4 days ago | |
| VHDL | Assembly | |
| BSD 3-clause "New" or "Revised" License | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
neorv32
Posts with mentions or reviews of neorv32.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-08.
- An example of how to add the A ISA extension's LR/SC operations into an open-source architecture
- NEORV32 - A tiny, customizable and highly extensible MCU-class 32-bit RISC-V microcontroller-like SoC written in platform-independent VHDL
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Recommendations for RISC-V on FPGA
How about NEORV32?
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
GitHub - stnolting/neorv32: 🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. this one is good but is written in VHDL though
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RISCV CPU using PL on Pynq Z2 Development Board
NEORV32 is an open source soft core and very well documented. I would recommend you to take a look at it and play around a bit. And it is certainly possible to have a soft core running on only the PL side without PS interference.
- A tiny 1-Wire controller for FPGAs (in VHDL)
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Anyone want to share some embedded projects they have done?
Maybe not a classic (whatever that means...) project, but I am working (together with others) on a RISC-V microcontroller for FPGAs: https://github.com/stnolting/neorv32
riscv-arch-test
Posts with mentions or reviews of riscv-arch-test.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-10-20.
- Starting my Final Year Project on Architectural Validation of a RISC-V Core
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Heed help with riscv-arch-test
git: https://github.com/riscv-non-isa/riscv-arch-test.git commit: 6d87f30 (current master)
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Available (official) test suite?
There's also https://github.com/riscv-non-isa/riscv-arch-test, which I think is using similar tests to riscof (some generated by riscv_ctg) just an older framework to run it all.
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Problems with riscv-arch-test
Prior notice, I work for a professor and he wants me to test/verify a riscv simulation model, which is programmed in VHDL. He referred to the https://github.com/riscv-non-isa/riscv-arch-test , to look up how I have to set up a test.
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Compliance tests official repository
This is the current compliance test repository. https://github.com/riscv-non-isa/riscv-arch-test
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I’m working on a Rust library to help learners of RISC-V, thought you folks may find it interesting!
Have you tried running the RISC-V architectural test suite: https://github.com/riscv/riscv-arch-test? It should fit pretty nicely with your test system, each test generates a signature that needs to be checked against an expected output.
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FPGA and Simulation tools for Risc-V design
There are official RISC V tests you can run: https://github.com/riscv/riscv-compliance
What are some alternatives?
When comparing neorv32 and riscv-arch-test you can also consider the following projects:
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscv-tests
linux-on-litex-vexriscv - Linux on LiteX-VexRiscv
riscv-formal - RISC-V Formal Verification Framework
picoMIPS - picoMIPS processor doing affine transformation
riscv-isa-sim - Spike, a RISC-V ISA Simulator
upduino-projects - Various VHDL projects I've worked on for the Upduino v2.0 and v3.0
rrs - Rust RISC-V Simulator
chipyard - An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
riscof
lxp32-cpu - A lightweight, open source and FPGA-friendly 32-bit CPU core based on an original instruction set
openarty - An Open Source configuration of the Arty platform
neorv32 vs VexRiscv
riscv-arch-test vs riscv-tests
neorv32 vs linux-on-litex-vexriscv
riscv-arch-test vs riscv-formal
neorv32 vs picoMIPS
riscv-arch-test vs riscv-isa-sim
neorv32 vs upduino-projects
riscv-arch-test vs rrs
neorv32 vs chipyard
riscv-arch-test vs riscof
neorv32 vs lxp32-cpu
riscv-arch-test vs openarty