rggen VS open-register-design-tool

Compare rggen vs open-register-design-tool and see what are their differences.

rggen

Code generation tool for control and status registers (by rggen)
Verilog Systemverilog Uvm Rtl Ral Csr soc Fpga Asic register-descriptions uvm-ral-model wiki-documents amba axi apb uvm-register-model eda Vhdl wishbone-bus
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open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input (by Juniper)
systemrdl jspec eda Asic Fpga registers Uvm Systemverilog register-descriptions systemrdl-compiler
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rggen open-register-design-tool
3 2
291 183
4.1% 0.5%
7.1 5.3
19 days ago 10 months ago
Ruby Verilog
MIT License Apache License 2.0
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

rggen

Posts with mentions or reviews of rggen. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-06-13.
  • RgGen v0.28.0
    1 project | /r/u_taichi730 | 11 Oct 2022
    I've released RgGen v0.28.0! https://github.com/rggen/rggen/releases/tag/v0.28.0 This release includes following updates.
  • RgGen update (support C header file generation)
    3 projects | /r/u_taichi730 | 13 Jun 2022
    RgGen is a code generation tool for configuration and status registers. RgGen can generate SV/Verilog/VHDL RTL, UVM RAL model and Markdown documents from readable register map specifications. https://github.com/rggen/rggen
  • RgGen update
    4 projects | /r/FPGA | 25 Mar 2022
    I just released the latest RgGen v0.26.0! https://github.com/rggen/rggen/releases/tag/v0.26.0

open-register-design-tool

Posts with mentions or reviews of open-register-design-tool. We have used some of these posts to build our list of alternatives and similar projects.
  • Thoughts about SystemRDL ?
    1 project | /r/FPGA | 8 Mar 2021
    I have used this compiler (https://github.com/Juniper/open-register-design-tool/wiki/Running-Ordt) to generate a Python model to access registers (I use Python on embedded Linux to read/write registers over SPI to the device).
  • Auto Generate Header Files
    1 project | /r/FPGA | 28 Jan 2021

What are some alternatives?

When comparing rggen and open-register-design-tool you can also consider the following projects:

PeakRDL-uvm - Generate UVM register model from compiled SystemRDL input

livehd - Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

PeakRDL-ipxact - Import and export IP-XACT XML register models

gf180mcu-pdk - PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).

vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

PeakRDL-html - Generate address space documentation HTML from compiled SystemRDL input

edalize - An abstraction library for interfacing EDA tools

OpenTimer - A High-performance Timing Analysis Tool for VLSI Systems

rggen-sv-rtl - Common SystemVerilog RTL modules for RgGen

biriscv - 32-bit Superscalar RISC-V CPU

hdlConvertor - Fast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4

axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

rggen vs PeakRDL-uvm open-register-design-tool vs livehd rggen vs PeakRDL-ipxact open-register-design-tool vs gf180mcu-pdk rggen vs vscode-terosHDL open-register-design-tool vs PeakRDL-html rggen vs edalize open-register-design-tool vs OpenTimer rggen vs rggen-sv-rtl open-register-design-tool vs biriscv rggen vs hdlConvertor open-register-design-tool vs axi