riscv-profiles
riscv-isa-manual
riscv-profiles | riscv-isa-manual | |
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21 | 41 | |
88 | 3,359 | |
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10 days ago | 2 days ago | |
Makefile | TeX | |
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riscv-profiles
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How to improve the RISC-V specification
Ssstrict is supposed to address the undefined behaviour problem, or at least it'll make undefined instructions actually trap.
https://github.com/riscv/riscv-profiles/blob/main/rva23-prof...
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Raspberry Pi receives strategic investment from Arm
>there are a lot of incompatible ISA implementations of RISC-V
This is common FUD.
In reality, most chips in the market, including all known application processors, follow the RVA profile[0] spec.
So do Linux distributions.
0. https://github.com/riscv/riscv-profiles/releases
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You Won’t Believe This One Weird CPU Instruction (2019)
The bit manipulation [0] extension has been ratified for a while now and is part of the RVA22 application extension profile [1].
You can already buy SOCs that support it, e.g. vision five 2 and star64.
Interestingly the risc-v vector has it's own popcount instructions for vector registers/register masks. This is needed, because the scalable architecture doesn't guarantee that a vector mask can fit into a 64 bit register, so vector masks are stored in a single LMUL=1 register. This works really well, because with LMUL=8 and SEW=8 you get 100% utilization of the single LMUL=1 vector register.
Another interesting thing is that the vector crypto extension will likely introduce a element wise popcount instruction.
[0] https://github.com/riscv/riscv-bitmanip/releases/download/1....
[1] https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
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The legend of "x86 CPUs decode instructions into RISC form internally"
That's why we have RISC-V profiles.
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Why is std::hardware_destructive_interference_size a compile-time constant instead of a run-time value?
Yeah more or less. They now have RISC-V Application Profiles which are basically minimum requirements for "application processors" - essentially devices like phones where you might want to distribute binary apps.
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RISC-V Profiles: Defining sets of extensions for coherent ecosystems
The Profiles spec which includes RVA22 was finally ratified[0] last week.
0. https://github.com/riscv/riscv-profiles/releases/tag/v1.0
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RISC-V Profiles
Context: RISC-V profiles spec got ratified last week.
- Questions about standard extensions
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RISC-V Business: Testing StarFive's VisionFive 2 SBC
Yeah unfortunately there isn't really a great place that lists all the extensions with links and ratification status.
But anyway there is a sort of standard set of extensions that "application processors" (I guess CPUs that want to run precompiled code) should support:
https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
The 22 indicates the year.
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TinyEMU – x86 and RISC-V emulator, small and simple while being complete
Ah, you're right: https://github.com/riscv/riscv-profiles/blob/main/profiles.a...
That's good to see. (Boy, it's really hard to find info about RISC-V profiles on Google. It just seems to ignore all the letters and numbers.)
riscv-isa-manual
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The Improved RISC-V Specification (latest WIP draft)
https://github.com/riscv/riscv-isa-manual/releases
Regarding the recent "How to improve the RISC-V specification" post [0], I just wanted to point out, that the latest draft manual is already a great improvement. (see link above)
It includes a lot of the newly ratified extensions: bitmanip,zicond,vector,vector crypto, ...
And there are a bunch of included SAIL definitions for bitmanip and zicond, but other instructions are still missing the SAIL code. Most notably, the SAIL definitions from the RV32I/RV64I base isa are also missing.
I asked for the further SAIL integration plans here: https://github.com/riscv/riscv-isa-manual/issues/1369
Here is an example SAIL snippet from cpopw:
let bitcount = 0;
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How to improve the RISC-V specification
I encourage you to look at the newest isa manual draft on github: https://github.com/riscv/riscv-isa-manual/releases
It includes the more recently extensions, and e.g. the bitmanip instructions all have associated pseudo code.
Here is e.g. the code for cpopw:
let bitcount = 0;
- Need help with designing a basic RISC V processor?
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The legend of “x86 CPUs decode instructions into RISC form internally”
I tried searching the spec [1] for "overflow" and here is what it says at page 17:
> We did not include special instruction-set support for overflow checks on integer arithmetic operations in the base instruction set, as many overflow checks can be cheaply implemented using RISC-V branches.
> For general signed addition, three additional instructions after the addition are required
Is this "cheap", replacing 1 instruction with four? According to some old mainframe era research (cannot find link now), addition is the most often used instruction and they suggest that we should replace each one with four?
Their "rationale" is not rational at all. It doesn't make sense.
Overflow check should be free (no additional instructions required), otherwise we will see the same story we have seen for last 50 years: compiler writers do not want to implement checks because they are expensive; language designers do not want to use proper arithmetic because it is expensive. As a result, there will be errors and vulnerabilities. A vicious circle.
[1] https://github.com/riscv/riscv-isa-manual/releases/download/...
- 64-bit Arm ∩ 64-bit RISC V
- Beginner question: F extension
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Riscv Ghidra Instruction Manual
Why not use the actual release PDF instead from their github? https://github.com/riscv/riscv-isa-manual
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How would I go about designing an 8-bit RISC-V CPU? Is it possible?
https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf Part 2
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Have to convert a C language code into RISC-V MIPS
If you don't want to cheat then read the RISC-V ISA manual: https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf
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How does a computer understand machine language?
Yeah you are on the right track. Processors are designed on top of an Instruction Set Architecture (ISA). For an example you can look on top of the RISC-V specifications:https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf (possible PDF download)
What are some alternatives?
riscv-platform-specs - RISC-V Profiles and Platform Specification
riscv-elf-psabi-doc - A RISC-V ELF psABI Document
xuantie-yocto - Yocto project for Xuantie RISC-V CPU
riscv-emulator-docker-image
openc906 - OpenXuantie - OpenC906 Core
amaranth - A modern hardware definition language and toolchain based on Python
riscv-v-spec - Working draft of the proposed RISC-V V vector extension
volk - The Vector Optimized Library of Kernels
vroom - VRoom! RISC-V CPU
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
open-source-cs - Video discussing this curriculum: