A simple AXI-Lite register file

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Fpga wishbone wishbone-bus axi-bus Xilinx

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  • wb2axip

    Bus bridges and other odds and ends

    • As an experiment, I tried a formal first approach using u/ZipCPU's faxil_slave.v.

  • InfluxDB

    Power Real-Time Data Analytics at Scale. Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.

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NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

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