darkriscv
opensouce RISC-V cpu core implemented in Verilog from scratch in one night! (by darklife)
Toast-RV32i
Pipelined RISC-V RV32I Core in Verilog (by georgeyhere)
| darkriscv | Toast-RV32i | |
|---|---|---|
| 3 | 2 | |
| 1,916 | 34 | |
| 1.0% | - | |
| 6.2 | 0.0 | |
| 9 days ago | about 1 year ago | |
| Verilog | C | |
| BSD 3-clause "New" or "Revised" License | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
darkriscv
Posts with mentions or reviews of darkriscv.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-08-20.
-
As an undergrad in my 3rd year with what feels like very little basics down, is implementing a basic RISC-V 5-stage pipelined processor on an FPGA too complex a project for an undergrad student?
This guy here has designed his 2 stage RISC-V in just one right: https://github.com/darklife/darkriscv.
- Are there any dual-GBE, PoE-capable SBCs?
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Chinese Academy of Sciences releases "Xiangshan", a high performance open source RISC-V processor that runs Linux
Just found https://github.com/darklife/darkriscv whose (incomplete) core is surprisingly short. Which means you won't have to learn a lot. You can run it in simulator or on one of the listed fpga boards.
Toast-RV32i
Posts with mentions or reviews of Toast-RV32i.
We have used some of these posts to build our list of alternatives
and similar projects.
- Intermediate FPGA project suggestions for resume
-
RV32i RISCV processor for resume - Suggestions/feedback?
Github: https://github.com/georgeyhere/Toast-RV32i
What are some alternatives?
When comparing darkriscv and Toast-RV32i you can also consider the following projects:
biriscv - 32-bit Superscalar RISC-V CPU
riscv - RISC-V CPU Core (RV32IM)
XiangShan - Open-source high-performance RISC-V processor
quasiSoC - Linux capable RISC-V SoC designed to be readable and useful.
spu32 - Small Processing Unit 32: A compact RV32I CPU written in Verilog
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
openwifi - open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software
Cores-VeeR-EH1 - VeeR EH1 core
RISCV - A Pipelined RISC-V RV32I Core in Verilog [Moved to: https://github.com/georgeyhere/Toast-RV32i]
friscv - RISCV CPU implementation in SystemVerilog
NyuziProcessor - GPGPU microprocessor architecture