ibex
picorv32
ibex | picorv32 | |
---|---|---|
21 | 16 | |
1,269 | 2,811 | |
2.0% | 1.5% | |
8.2 | 5.2 | |
2 days ago | 2 months ago | |
SystemVerilog | Verilog | |
Apache License 2.0 | ISC License |
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ibex
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RISC-V support in Android just got a big setback
> Right now, most devices on the market do not support the C extension
This is not true and easily verifiable.
The C extension is defacto required, the only cores that don't support it are special purpose soft cores.
C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file
Supports M and C extensions https://github.com/YosysHQ/picorv32
Another sized optimized core with C extension support https://github.com/lowrisc/ibex
C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html
This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
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Major Changes at RISC-V Designer SiFive
We've had people consider Ibex for space applications, well verified and has a dual-core lockstep option: https://github.com/lowRISC/ibex.
An ETH Zurich team have done a triple core lockstep version for cubesats: https://www.theregister.com/2023/10/05/riscv_microcontroller...
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Hot Chips 2023: SiFive’s P870 Takes RISC-V Further
I definitely agree with the primary point, "building a chip that meets specfic requirements we got from the customer" is not easy and it what matters.
However, RISCV cores abound. In pretty much any computing language known to man with varying design trade-offs and capabilities. It's extremely difficult to differentiate at the RTL level at this time.
Here is a high quality, well documented, SystemVerilog version intended for embedded applications that I know has been included in multiple ASIC and FPGA designs successfully.
https://github.com/lowRISC/ibex
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Looking to work in Open Source Silicon and RISC-V? lowRISC is hiring DV and infrastructure engineers
lowRISC's (www.lowrisc.org) mission is to bring open source silicon to the hardware world and see it shipping in volume in commercial applications. We want to see open source silicon occupy a similar position to open source software (e.g. look at Linux, it's the default choice in many applications, we'd like open source silicon to be used for similar foundational technologies in the hardware world).
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How to use verilator to transfer a design with multiple files to a verilated model?
Here I will just use Ibex, a risc-v processor as an example, of which the repository is here: lowrisc_ibex. There are many files in this repository and I wonder which files I need given a specific configuration (for example, the configuration of "maxperf"), and how I can combine all the necessary files together, feed them to verilator and get its verilated model? I understand that only by going through this step will I acquire necessary C++ header files to write the testbench
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Ushering In a New Era for Open-Source Silicon Development (CEO of lowrisc , a non profit that develops open source hardware on why open source hardware failed in the past, and how lowrisc does things differently)
i think it might be worth it to post it here because lowrisc develops ibex (a open source risc-v core).
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What is to be gained from ISA convergence on all levels of computing?
Yeah but you can have both an open source (e.g. ibex) and closed source implementations for controllers (the open source one is free and you can improve it and even close its source so competitors won't benefit from your improvements) , and you can migrate from one supplier to another without spending a lot of money on migrating the software.
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synthesizing and using the Ibex RISC-V core
I am pretty new to RISC-V and open-source hardware and just began learning and working with them as part of my research. I searched about different models that have some credible documents and research done into them and decided I would try and use the ibex as the hardware language is easier for me to follow too.
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RISC-V Pushes into the Mainstream
Ibex is open source and has taped out - https://github.com/lowRISC/ibex
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RISC-V simulator
That said we used Spike as a reference simulator for verifying Ibex (RISC-V core I work on, https://github.com/lowRISC/ibex) and we run an extensive set of random programs through it comparing its execution to Ibex's and I've not come across any major issues.
picorv32
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RISC-V support in Android just got a big setback
> Right now, most devices on the market do not support the C extension
This is not true and easily verifiable.
The C extension is defacto required, the only cores that don't support it are special purpose soft cores.
C extension in the smallest IP available core https://github.com/olofk/serv?tab=readme-ov-file
Supports M and C extensions https://github.com/YosysHQ/picorv32
Another sized optimized core with C extension support https://github.com/lowrisc/ibex
C extension in the 10 cent microcontroller https://www.wch-ic.com/products/CH32V003.html
This one should get your goat, it implements as much as it can using only compressed instructions https://github.com/gsmecher/minimax
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SPI PROTOCOL in FPGA
In contrast to most people here saying you NEED to spend money. I disagree with that. You can implement and simulate a SPI master/slave fully on your computer, no FPGA or other hardware required. There are simulation models for SPI peripherals you could use. For example: https://github.com/YosysHQ/picorv32/blob/master/picosoc/spiflash.v
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How many gates does a decent risc-v implementation take?
The Pico RV32 is pretty small, and can go as low as about 750 LUTs, with most features elided. I don't know how Xilinix LUTs translate to Lattice though.
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Open-source RISC-V CPU projects for contribution
Picorv32: https://github.com/YosysHQ/picorv32
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We ran a Unix-like OS (Xv6) on our home-built CPU with our home-built C compiler
There are loads of free RISC-V cores that you can read the source of and run on cheap FPGAs. Take a look at PicoRV32: https://github.com/YosysHQ/picorv32
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SUGGEST AN OPEN SOURCE RISC-V CORE DESIGNED IN VERILOG
picorv32 is written in Verilog.
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Minimax: a Compressed-First, Microcoded RISC-V CPU
In short: it works, though the implementation lacks the crystal clarity of FemtoRV32 and PicoRV32. The core is larger than SERV but has higher IPC and (very arguably) a more conventional implementation. The compressed instruction set is easier to expand into regular RV32I instructions than it is to execute directly.
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Apple to Move a Part of Its Embedded Cores to RISC-V
That is, reducing the number of LUT required to implement a CPU of a given ISA.
A basic RV32 CPU is down to 500-700 LUT.
https://github.com/YosysHQ/picorv32
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Designing a reasonable memory interface
I've bought a cheap FPGA board (Sipeed Tang Nano 9K) because I want to implement a little 8 or 16-bit CPU. The FPGA has plenty of BRAM for such a little CPU, so I wouldn't even need to implement an SPI controller initially, but I want to implement a von Neumann architecture, and was wondering if the only way of doing so using single port (or semi dual port) RAM would be to use 2 cycles or more for memory transfer operations (one for loading the instruction, one for executing the actual memory transfer), or if there was any technique that could be used to avoid this without having to implement instruction-level parallelism. Even if not, references to understandable code implementing a simple memory interface would be appreciated. I looked at PicoRV32 but couldn't really understand its inner workings.
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Risc-v rv32i softcore processor for Zybo-z7-10
Have you looked at PicoRV32? https://github.com/YosysHQ/picorv32
What are some alternatives?
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
opentitan - OpenTitan: Open source silicon root of trust
neorv32-setups - 📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
tomverbeure
rocket-chip - Rocket Chip Generator
riscv-isa-manual - RISC-V Instruction Set Manual
skywater-pdk - Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
neorv32 - :desktop_computer: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
wd65c02 - Cycle accurate FPGA implementation of various 6502 CPU variants
lowrisc-chip - The root repo for lowRISC project and FPGA demos.
Projects - Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. MCL51, MCL64, MCL65, MCL65+, MCL68, MCL86, MCL86+, MCL86jr, MCLR5, MCLZ8