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Mentions
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Stars | Project | Description |
|---|---|---|---|
| 21 | 1,250 | Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. | |
| 1 | 4,303 | A minimal GPU design in Verilog to learn how GPUs work from the ground up | |
| 1 | 42 | FPGA exercise for beginners |
Popular SystemVerilog Topics
Latest Mentions
Latest mentioned SystemVerilog repos
| Stars | Project |
|---|---|
| 1,250 | ibex |
| 4,303 | tiny-gpu |
| 42 | basics-graphics-music |
| 13 | ebrick-demo |
| 1 | PurdNyUart |
| 6 | GettingVerilatorStartedWithUVM |
| 57 | FazyRV |
| 1,008 | hdmi |
| 2,357 | opentitan |
| 61 | sargantana |
| 2 | petalinux_notes |
| 1 | RTLDesignSherpa |
| 34 | MacPlus_MiSTer |
| 106 | analogue-pocket-utils |
| 2 | ulm-on-ice |
| 1 | NeuralNetworkOnFPGA |
| 152 | Saturn_MiSTer |
| 784 | swerv_eh1 |
| 57 | cheriot-ibex |
| 3 | Verilog-SystemVerilog |
Latest Discoveries
Latest discovered SystemVerilog repos
| Stars | Project |
|---|---|
| 42 | basics-graphics-music |
| 4,303 | tiny-gpu |
| 13 | ebrick-demo |
| 6 | GettingVerilatorStartedWithUVM |
| 57 | FazyRV |
| 61 | sargantana |
| 2 | petalinux_notes |
| 1 | RTLDesignSherpa |
| 2 | ulm-on-ice |
| 1 | NeuralNetworkOnFPGA |
| 152 | Saturn_MiSTer |
| 57 | cheriot-ibex |
| 3 | Verilog-SystemVerilog |
| 61 | CX |
| 0 | osdr-q10 |
| 53 | fpga-gameandwatch |
| 4 | AI-Robotics |
| 1 | PurdNyUart |
| 6 | fpga_screensaver |
| 1 | VGA-SRAM |
Recently updated posts
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Tiny GPU: A minimal GPU implementation in Verilog
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Show HN: Build Your Own Chip
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FazyRV – A Scalable RISC-V Core
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SNESTang – SNES for Sipeed Tang Primer 25K FPGA Board
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Need a teacher for Zynq SoC