SystemVerilog Posts

Latest SystemVerilog related posts with mentions of open-source projects
  • A simple superscalar out of order RISC-V (micro)processor

    1 project | news.ycombinator.com | 2 days ago
  • Tiny GPU: A minimal GPU implementation in Verilog

    3 projects | news.ycombinator.com | 27 days ago
  • Show HN: Build Your Own Chip

    1 project | news.ycombinator.com | 2 months ago
  • FazyRV – A Scalable RISC-V Core

    1 project | news.ycombinator.com | 3 months ago
  • SNESTang – SNES for Sipeed Tang Primer 25K FPGA Board

    1 project | news.ycombinator.com | 5 months ago
  • Need a teacher for Zynq SoC

    1 project | /r/FPGA | 5 months ago
  • Weighted round robin

    1 project | /r/FPGA | 6 months ago
  • Making a Macintosh Plus Clone

    4 projects | /r/VintageApple | 6 months ago
  • FPGAs and the Renaissance of Retro Hardware

    2 projects | news.ycombinator.com | 6 months ago
  • Major Changes at RISC-V Designer SiFive

    1 project | news.ycombinator.com | 7 months ago
  • Building your own computer with an FPGA

    1 project | /r/FPGA | 7 months ago
  • Review on a starter project about a NN on an FPGA

    1 project | /r/FPGA | 8 months ago
  • Sega Saturn Mini Could Become a Reality, Thanks to Retron FPGA

    1 project | news.ycombinator.com | 8 months ago
  • Arm IPO to kick off today with company valued at $54.5B

    1 project | news.ycombinator.com | 8 months ago
  • What’s the Smallest Variety of CHERI? (2022)

    1 project | news.ycombinator.com | 8 months ago
  • Hot Chips 2023: SiFive’s P870 Takes RISC-V Further

    1 project | news.ycombinator.com | 9 months ago
  • Basic UART implementation in UART

    1 project | /r/FPGA | 9 months ago
  • Design and Rationale of the RISC-V Composable Custom Extensions Specification [video]

    1 project | news.ycombinator.com | 10 months ago
  • Verilator - Do I need to maintain two testbench suits?

    2 projects | /r/FPGA | 11 months ago
  • agg23/fpga-gameandwatch: Game and Watch for Analogue Pocket and MiSTer

    1 project | /r/MiSTerFPGA | 11 months ago
  • Interpreter on an FPGA?

    1 project | /r/FPGA | 11 months ago
  • Putting out the hardware dumpster fire

    1 project | news.ycombinator.com | 11 months ago
  • Looking to work in Open Source Silicon and RISC-V? lowRISC is hiring DV and infrastructure engineers

    2 projects | /r/FPGA | 11 months ago
  • They just pirated my open source 8088 BIOS

    2 projects | news.ycombinator.com | 11 months ago
  • building pulpissimo

    1 project | /r/chipdesign | 11 months ago
  • C++ Verification Testbench Best-Practice Resources?

    2 projects | /r/ECE | 12 months ago
  • Best fpga for begginers

    1 project | /r/FPGA | 12 months ago
  • CPU Design Verification Interview

    1 project | /r/ECE | 12 months ago
  • How to use verilator to transfer a design with multiple files to a verilated model?

    1 project | /r/ZipCPU | 12 months ago
  • SDRAM/DDR

    1 project | /r/Verilog | 12 months ago
  • Help with a SPI protocol using verilog!!

    1 project | /r/Verilog | 12 months ago
  • How to design a more elegant and simple instraction decoder

    1 project | /r/RISCV | 12 months ago
  • How hard would it be to write fractional 0-1 informational states in different media off the shelf (RAM, HDD, SSD, etc? And w/ controller hacks allowed?)

    1 project | /r/hardware | almost 1 year ago
  • 432-Core Chiplet-Based RISC-V Chip Nearly Ready to Blast Into Space

    3 projects | /r/RISCV | about 1 year ago
  • Best tutorial on DDR protocol

    3 projects | /r/FPGA | about 1 year ago
  • 432-Core RISC-V European Processor Designed for Use in Space Taped Out

    1 project | news.ycombinator.com | about 1 year ago
  • Cpu project

    2 projects | /r/RISCV | about 1 year ago
  • Show HN: Tamagotchi P1 for FPGAs

    1 project | news.ycombinator.com | about 1 year ago
  • Ushering In a New Era for Open-Source Silicon Development (CEO of lowrisc , a non profit that develops open source hardware on why open source hardware failed in the past, and how lowrisc does things differently)

    1 project | /r/RISCV | about 1 year ago
  • Tamagotchi for FPGA

    1 project | news.ycombinator.com | about 1 year ago
  • Atari 800XL Remake

    1 project | news.ycombinator.com | about 1 year ago
  • What is to be gained from ISA convergence on all levels of computing?

    1 project | /r/RISCV | about 1 year ago
  • verilog-ext: Verilog Extensions for Emacs

    1 project | /r/planetemacs | about 1 year ago
  • How to read and write data from SD card?

    1 project | /r/GowinFPGA | about 1 year ago
  • SPI master driver for spi slave

    1 project | /r/FPGA | over 1 year ago
  • SPI master driver for spi slave

    1 project | /r/ElectricalEngineering | over 1 year ago
  • FPGA - DS3231 interface

    1 project | /r/Verilog | over 1 year ago
  • I want to learn to interface HDMI to Xilinx Kintex 7 FPGA. Can you please provide any resources? I don't have prior experience in interfacing HDMI.

    1 project | /r/FPGA | over 1 year ago
  • I attempted to design an FIR FILTER in systemverilog. It has a changeable coefficients with a update signal. I’d love your comments reviewing mine, and suggestions to improve.

    1 project | /r/FPGA | over 1 year ago
  • Ending this debate once and for all.

    1 project | /r/ProgrammerHumor | over 1 year ago