Introducing CoHDL

This page summarizes the projects mentioned and recommended in the original post on /r/FPGA

Scout Monitoring - Free Django app performance insights with Scout Monitoring
Get Scout setup in minutes, and let us sweat the small stuff. A couple lines in settings.py is all you need to start monitoring your apps. Sign up for our free tier today.
www.scoutapm.com
featured
InfluxDB - Power Real-Time Data Analytics at Scale
Get real-time insights from all types of time series data with InfluxDB. Ingest, query, and analyze billions of data points in real-time with unbounded cardinality.
www.influxdata.com
featured
  • cohdl

    A Python to VHDL compiler

  • Over the past few months, I have been working on CoHDL, a hardware description language embedded in Python. Similar to existing solutions like MyHDL, it works by inspecting and translating the abstract syntax tree of Python functions. The initial idea was to explore whether async/await coroutines could be used as an abstraction for state machines.

  • cocotb

    cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

  • At the moment, it is not possible to directly simulate synthesizable contexts. In principle, I could add a simulator to CoHDL. As a Python implementation, it would be orders of magnitude slower than other solutions. Instead, I am using Cocotb to validate the generated VHDL and for the unit tests in the GitHub repository. There is also some very, very experimental support for formal verification, but it will take some time for that to become usable.

  • Scout Monitoring

    Free Django app performance insights with Scout Monitoring. Get Scout setup in minutes, and let us sweat the small stuff. A couple lines in settings.py is all you need to start monitoring your apps. Sign up for our free tier today.

    Scout Monitoring logo
  • yieldfsm

    YieldFSM, a DSL for describing finite state machines in Clash

  • Nice! Need to check this out, CoHDL seems to have similarities to my work (https://dl.acm.org/doi/abs/10.1145/3549821, https://github.com/tilk/yieldfsm ).

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a more popular project.

Suggest a related project

Related posts

  • Lion: A formally verified, 5-stage pipeline RISC-V core

    2 projects | news.ycombinator.com | 4 Mar 2021
  • Designing a Low Latency 10G Ethernet Core

    2 projects | /r/FPGA | 4 Jul 2023
  • How is Python used in test automation in embedded systems?

    2 projects | /r/embedded | 19 Apr 2023
  • Use cocotb to test and verify chip designs in Python

    1 project | /r/cocotb | 12 Apr 2023
  • Trying to learn and work with FPGAs

    4 projects | /r/FPGA | 12 Apr 2023