Python Verilog

Open-source Python projects categorized as Verilog
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Topics: Vhdl Fpga Python Systemverilog Rtl
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Top 14 Python Verilog Projects

  • cocotb

    cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

    • Project mention: Designing a Low Latency 10G Ethernet Core | /r/FPGA | 2023-07-04

    The use of cocotb and pyuvm for verification

  • openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

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  • fusesoc

    Package manager and build abstraction tool for FPGA/ASIC development

    • Project mention: fusesoc VS vextproj - a user suggested alternative | libhunt.com/r/fusesoc | 2024-03-28

  • edalize

    An abstraction library for interfacing EDA tools

  • pymtl3

    Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

    • Project mention: Firrtl – Flexible Intermediate Representation for RTL | news.ycombinator.com | 2023-07-15

  • hdl_checker

    Repurposing existing HDL tools to help writing better code

  • sphinxcontrib-hdl-diagrams

    Sphinx Extension which generates various types of diagrams from Verilog code.

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  • vcdvcd

    Python Verilog value change dump (VCD) parser library + the nifty vcdcat VCD command line pretty printer.

  • cocotb-bus

    Pre-packaged testbenching tools and reusable bus interfaces for cocotb

  • naja

    Structural Netlist API (and more) for EDA post synthesis flow development

    • Project mention: Naja-Verilog: stand-alone structural (gate-level) parser | /r/FPGA | 2023-10-11

    Hi everyone, If you need to build C++ (or Python) application loading gate level verilog, similar to the one at the input of FPGA PnR tools, https://github.com/xtofalex/naja-verilog is available. This parser has been designed to allow the construction on the fly of any netlist data structure. One note: if you need also a C++ netlist data structure (with Python bindings) to build netlist analysis or editing tools on top, Naja SNL: https://github.com/xtofalex/naja is also ready for use. Hope this is useful. If it is or if you face any issue, please reach to me. Feedback welcome.

  • PyChip-py-hcl

    A Hardware Construct Language

  • deepsocflow

    An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

  • teroshdl-documenter-demo

    This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI workflow.

  • eda-log-file-warning-suppressor

    Suppresses warnings in EDA logfiles.

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Python Verilog related posts

  • Designing a Low Latency 10G Ethernet Core

    2 projects | /r/FPGA | 4 Jul 2023

  • Interactive Chess on Factorio CPU

    9 projects | /r/factorio | 5 May 2023

  • Introducing CoHDL

    5 projects | /r/FPGA | 15 Apr 2023

  • How is Python used in test automation in embedded systems?

    2 projects | /r/embedded | 19 Apr 2023

  • Use cocotb to test and verify chip designs in Python

    1 project | /r/cocotb | 12 Apr 2023

  • Trying to learn and work with FPGAs

    4 projects | /r/FPGA | 12 Apr 2023

  • Help understanding how this makefile works?

    1 project | /r/learnprogramming | 7 Feb 2023
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Index

What are some of the best open-source Verilog projects in Python? This list will help you:

Project Stars
1 cocotb 1,643
2 openlane 1,223
3 fusesoc 1,128
4 edalize 597
5 pymtl3 354
6 hdl_checker 185
7 sphinxcontrib-hdl-diagrams 52
8 vcdvcd 49
9 cocotb-bus 46
10 naja 46
11 PyChip-py-hcl 38
12 deepsocflow 40
13 teroshdl-documenter-demo 10
14 eda-log-file-warning-suppressor 2

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