Top 41 Trending Verilog Projects
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OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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MacroPlacement
Macro Placement - benchmarks, evaluators, and reproducible results from leading methods in open source
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CFU-Playground
Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.github.io/CFU-Playground/ For reference docs, see the link below.
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open-register-design-tool
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
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tillitis-key1
Board designs, FPGA verilog, firmware for TKey, the flexible and open USB security key š
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icebreaker-verilog-examples
This repository contains small example designs that can be used with the open source icestorm flow.
Index
What are some of the trending open-source Verilog projects? This list will help you:
Project | Growth | |
---|---|---|
1 | umi | 8.4% |
2 | or1200 | 6.5% |
3 | vortex | 6.1% |
4 | OpenROAD-flow-scripts | 5.9% |
5 | hw | 3.7% |
6 | ao486_MiSTer | 3.7% |
7 | iob-soc | 3.5% |
8 | OpenROAD | 3.1% |
9 | NeoGeo_MiSTer | 2.8% |
10 | corundum | 2.8% |
11 | MacroPlacement | 2.5% |
12 | openc910 | 2.4% |
13 | filament | 2.3% |
14 | livehd | 2.0% |
15 | icebreaker-workshop | 1.8% |
16 | apicula | 1.6% |
17 | OpenFPGA | 1.6% |
18 | uhd | 1.5% |
19 | betrusted-soc | 1.5% |
20 | picorv32 | 1.5% |
21 | apio | 1.3% |
22 | SCALE-MAMBA | 1.2% |
23 | hdl | 1.1% |
24 | CFU-Playground | 1.1% |
25 | darkriscv | 1.0% |
26 | C64_MiSTer | 0.9% |
27 | openc906 | 0.7% |
28 | OpenTimer | 0.6% |
29 | open-register-design-tool | 0.5% |
30 | f4pga-examples | 0.4% |
31 | tillitis-key1 | 0.3% |
32 | freepdk-45nm | 0.0% |
33 | miaow | 0.0% |
34 | fpga | 0.0% |
35 | icebreaker-verilog-examples | 0.0% |
36 | mipsfpga-plus | 0.0% |
37 | SOFA | 0.0% |
38 | riscv-formal | 0.0% |
39 | wujian100_open | 0.0% |
40 | netfpga | 0.0% |
41 | Minimig-AGA_MiSTer | -0.7% |