Python Rtl

Open-source Python projects categorized as Rtl
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Topics: Verilog Python Hdl Systemverilog yosys
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Top 6 Python Rtl Projects

  • openlane

    OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

  • Salamandra

    Salamandra is a tool to find spy microphones that use radio freq to transmit. It uses SDR.

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  • pymtl3

    Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

    • Project mention: Firrtl – Flexible Intermediate Representation for RTL | news.ycombinator.com | 2023-07-15

  • sphinxcontrib-hdl-diagrams

    Sphinx Extension which generates various types of diagrams from Verilog code.

  • PyChip-py-hcl

    A Hardware Construct Language

  • fsm2sv

    SystemVerilog FSM generator

NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

Python Rtl related posts

  • Cascade: CPU Fuzzing via Intricate Program Generation

    3 projects | news.ycombinator.com | 23 Oct 2023

  • Why are there only 3 languages for FPGA development?

    5 projects | /r/FPGA | 1 Dec 2022

  • Choice of Python HDL library

    10 projects | /r/FPGA | 25 Jul 2022

  • Suggest advance project ideas

    3 projects | /r/FPGA | 3 Sep 2021

Index

What are some of the best open-source Rtl projects in Python? This list will help you:

Project Stars
1 openlane 1,223
2 Salamandra 817
3 pymtl3 354
4 sphinxcontrib-hdl-diagrams 52
5 PyChip-py-hcl 38
6 fsm2sv 21

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