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Mentions
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Stars | Project | Description |
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21 | 1,261 | Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy. | |
1 | 5,880 | A minimal GPU design in Verilog to learn how GPUs work from the ground up | |
1 | 43 | FPGA exercise for beginners | |
1 | 1 | ableC extension for algebraic data types with C++-style templating |
Popular SystemVerilog Topics
Latest Mentions
Latest mentioned SystemVerilog repos
Stars | Project |
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1 | ableC-template-algebraic-data-types |
1,261 | ibex |
43 | basics-graphics-music |
5,880 | tiny-gpu |
13 | ebrick-demo |
1 | PurdNyUart |
6 | GettingVerilatorStartedWithUVM |
60 | FazyRV |
1,021 | hdmi |
2,371 | opentitan |
62 | sargantana |
2 | petalinux_notes |
1 | RTLDesignSherpa |
34 | MacPlus_MiSTer |
107 | analogue-pocket-utils |
2 | ulm-on-ice |
1 | NeuralNetworkOnFPGA |
153 | Saturn_MiSTer |
784 | swerv_eh1 |
59 | cheriot-ibex |
Latest Discoveries
Latest discovered SystemVerilog repos
Stars | Project |
---|---|
1 | ableC-template-algebraic-data-types |
43 | basics-graphics-music |
5,880 | tiny-gpu |
13 | ebrick-demo |
6 | GettingVerilatorStartedWithUVM |
60 | FazyRV |
62 | sargantana |
2 | petalinux_notes |
1 | RTLDesignSherpa |
2 | ulm-on-ice |
1 | NeuralNetworkOnFPGA |
153 | Saturn_MiSTer |
59 | cheriot-ibex |
3 | Verilog-SystemVerilog |
61 | CX |
0 | osdr-q10 |
53 | fpga-gameandwatch |
4 | AI-Robotics |
1 | PurdNyUart |
6 | fpga_screensaver |
Recently updated posts
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Tiny GPU: A minimal GPU implementation in Verilog
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Show HN: Build Your Own Chip
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FazyRV – A Scalable RISC-V Core
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SNESTang – SNES for Sipeed Tang Primer 25K FPGA Board
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Need a teacher for Zynq SoC