SystemVerilog Rtl

Open-source SystemVerilog projects categorized as Rtl
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Topics: Axi4 Systemverilog Riscv Fpga risc-v
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Top 7 SystemVerilog Rtl Projects

  • axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

  • scr1

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

  • InfluxDB

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  • Cores-VeeR-EH1

    VeeR EH1 core

  • Cores-VeeR-EL2

    VeeR EL2 Core

  • rggen-sv-rtl

    Common SystemVerilog RTL modules for RgGen

  • Arithmetic-Circuits

    This repository contains different modules which execute arithmetic operations. (by GabbedT)

  • RTLDesignSherpa

    This site is hopefully a springboard for others to learn about coding in System Verilog and experimenting with FPGAs.

    • Project mention: Weighted round robin | /r/FPGA | 2023-12-07

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NOTE: The open source projects on this list are ordered by number of github stars. The number of mentions indicates repo mentiontions in the last 12 Months or since we started tracking (Dec 2020).

SystemVerilog Rtl related posts

  • The Surprising Subtleties of Zeroing a Register

    3 projects | news.ycombinator.com | 4 Nov 2021

  • Mikron MIK32 – Made in Russia 32-bit RISC-V MCU... for about $6

    1 project | /r/RISCV | 10 Sep 2021

  • RSD is a open source high performance RISC-V Processor

    3 projects | /r/linux | 4 Jan 2021

Index

What are some of the best open-source Rtl projects in SystemVerilog? This list will help you:

Project Stars
1 axi 937
2 scr1 776
3 Cores-VeeR-EH1 776
4 Cores-VeeR-EL2 222
5 rggen-sv-rtl 11
6 Arithmetic-Circuits 3
7 RTLDesignSherpa 1

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